Based on the more request of the semiconductor package, a multi-chip package is developed for assembling a plurality of chips which having the same or different functions to make a system in package (SIP). According the different types of the chips, the multi-chip package assembles several kinds of chips by wire-bonding and flip-chip connection.
R.O.C. Taiwan Patent No. 466719 entitled “multi chip module packaging method by mixing chip and package” disclosed a multi-chip module package. An encapsulating material on a substrate seals a wire-bonding chip and a chip scale package. The chip scale package is flip-chip mounted on the substrate, which includes a chip and a sub-package body. After mounting the chip scale package and the wire-bonding chip on the substrate, the encapsulating material seals the chip scale package and the wire-bonding chip by molding. To seal the chip scale package the substrate should have a larger dimension. In addition, the chip scale package is sealed inside the encapsulating material, so the chip scale package cannot be reworked after molding. When the functions test result of the multi-chip module package is NG, the whole package has to be scrapped. If the chip scale package is designed outside the encapsulating material, the plurality of contact pads on the substrate for electrically connecting the chip scale package are easily damaged by a molding tool for molding the encapsulating material, especially there is pre-solder printed on the contact pads. It would easily cause the substrate warpage.